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Raspberry Pi /RP2350 /CLOCKS /SLEEP_EN0

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Interpret as SLEEP_EN0

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https://regviz.com/r/Raspberry Pi/RP2350/CLOCKS/SLEEP_EN0#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CLK_SYS_CLOCKS)CLK_SYS_CLOCKS 0 (CLK_SYS_ACCESSCTRL)CLK_SYS_ACCESSCTRL 0 (CLK_ADC)CLK_ADC 0 (CLK_SYS_ADC)CLK_SYS_ADC 0 (CLK_SYS_BOOTRAM)CLK_SYS_BOOTRAM 0 (CLK_SYS_BUSCTRL)CLK_SYS_BUSCTRL 0 (CLK_SYS_BUSFABRIC)CLK_SYS_BUSFABRIC 0 (CLK_SYS_DMA)CLK_SYS_DMA 0 (CLK_SYS_GLITCH_DETECTOR)CLK_SYS_GLITCH_DETECTOR 0 (CLK_HSTX)CLK_HSTX 0 (CLK_SYS_HSTX)CLK_SYS_HSTX 0 (CLK_SYS_I2C0)CLK_SYS_I2C0 0 (CLK_SYS_I2C1)CLK_SYS_I2C1 0 (CLK_SYS_IO)CLK_SYS_IO 0 (CLK_SYS_JTAG)CLK_SYS_JTAG 0 (CLK_REF_OTP)CLK_REF_OTP 0 (CLK_SYS_OTP)CLK_SYS_OTP 0 (CLK_SYS_PADS)CLK_SYS_PADS 0 (CLK_SYS_PIO0)CLK_SYS_PIO0 0 (CLK_SYS_PIO1)CLK_SYS_PIO1 0 (CLK_SYS_PIO2)CLK_SYS_PIO2 0 (CLK_SYS_PLL_SYS)CLK_SYS_PLL_SYS 0 (CLK_SYS_PLL_USB)CLK_SYS_PLL_USB 0 (CLK_REF_POWMAN)CLK_REF_POWMAN 0 (CLK_SYS_POWMAN)CLK_SYS_POWMAN 0 (CLK_SYS_PWM)CLK_SYS_PWM 0 (CLK_SYS_RESETS)CLK_SYS_RESETS 0 (CLK_SYS_ROM)CLK_SYS_ROM 0 (CLK_SYS_ROSC)CLK_SYS_ROSC 0 (CLK_SYS_PSM)CLK_SYS_PSM 0 (CLK_SYS_SHA256)CLK_SYS_SHA256 0 (CLK_SYS_SIO)CLK_SYS_SIO

Description

enable clock in sleep mode

Fields

CLK_SYS_CLOCKS
CLK_SYS_ACCESSCTRL
CLK_ADC
CLK_SYS_ADC
CLK_SYS_BOOTRAM
CLK_SYS_BUSCTRL
CLK_SYS_BUSFABRIC
CLK_SYS_DMA
CLK_SYS_GLITCH_DETECTOR
CLK_HSTX
CLK_SYS_HSTX
CLK_SYS_I2C0
CLK_SYS_I2C1
CLK_SYS_IO
CLK_SYS_JTAG
CLK_REF_OTP
CLK_SYS_OTP
CLK_SYS_PADS
CLK_SYS_PIO0
CLK_SYS_PIO1
CLK_SYS_PIO2
CLK_SYS_PLL_SYS
CLK_SYS_PLL_USB
CLK_REF_POWMAN
CLK_SYS_POWMAN
CLK_SYS_PWM
CLK_SYS_RESETS
CLK_SYS_ROM
CLK_SYS_ROSC
CLK_SYS_PSM
CLK_SYS_SHA256
CLK_SYS_SIO

Links

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Register License

Copyright © 2024 Raspberry Pi Ltd.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data